Note

A post I wrote a while ago and then got very busy and never published, stock is now very easy to get of these.

Introduction

Finally these came into stock and I managed to get some from Farnell, they appear to arrive in small batches and then go out of stock in a matter of hours. For those who do not know this is a small ARM Cortex M0+ in an 8pin DIP package. It has 4K Flash, 1K RAM, it also has an 8K ROM which contains a boot loader and some driver code for some of the on chip peripherals.

I started with the LPC810_Codebase on github (https://github.com/microbuilder/LPC810_CodeBase) but quickly decided there where too many magic numbers, to understand any of the code you needed the data sheet constantly.

The alternative was the driver package provided with lpxexpresso, there where complaints that this was bloated but I found a half way house. I use the include files but not the library C source files. So I have access to all the named constants and the inline code functions (these generally are single C statements to set a flag etc.). This also means when I am trying to test something I can switch quickly to using a function in the driver library and see whether that works. Yes the code is bloated as it pulls lots in, for example a simple piece of code that blinks an LED and sends characters on the USART, if I use the driver code to set the USART up it adds circa 800bytes of code. This is because it ends up pulling in code to work out which system clock you are on etc.

Configuring baud rates.

The LPC8xx have a fractional rate prescaler that generates the clock to each USART baud rate generator. This enables you to get close tollerance baud rate generation. The other thing to watch is that the input to the fractional rate prescaler is not the system clock but comes before the system dividor. For example in this case the internal clock runs at 12Mhz and is fed through the PLL to get 60Mhz this is then divided by 2 to get a 30Mhz processor system clock. I found that a dividor of 1.25 gives a good basis to generate clocks from 9600 to 250000 (DMX controller) with less than 0.2% error in the generetaed clock. Combine this with the Internal clock tolerance (1%) and you stay within the 2% recommnded for reliable asynchronous communications.

Sample values

These are based on using the internal RC oscilator fed through the PLL to generate a 60Mhz master clock.

Fractional rate setup.

LPC_SYSCTL->UARTCLKDIV = 1; LPC_SYSCTL->UARTFRGDIV = 255; LPC_SYSCTL->UARTFRGMULT = 64;

The gotcha I got was the compiler doing 32 bit arithmatic so when you use the common equation you end up with integer overflow.

// With 30Mhz master oscilattor #define UART_MASTER_DIV 1 #define UART_FRG_DIV 256 #define UART_FRG_MUL 64 // This needed reordering as compiler does 32 bit integer arithmatic // Then the top half overflows as well. //#define U_PCLK (((__MAIN_CLOCK/UART_MASTER_DIV)*UART_FRG_DIV)/(UART_FRG_DIV+UART_FRG_MUL)) // So simplified #define U_PCLK ((__MAIN_CLOCK/UART_MASTER_DIV)*4/5)

#define BRGVAL(baud) (((U_PCLK/16)/baud)-1)